2021-10-03 22:48 电子科技大学 FPGA工程师

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秋招——芯原笔试

总览
- 往年试题
- 2022届试题

总览

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往年试题

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A B的侧边梯形三等分和两等分线不应该重合。

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\frac{1}{{}^{1}\!\!\diagup\!\!{}_{2}\;\bullet \left( {}^{1}\!\!\diagup\!\!{}_{300}\;+{}^{1}\!\!\diagup\!\!{}_{450}\; \right)}

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D 外面等于里面所有的和

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GPU: GPU(Graphic Processing Unit)是图形处理器，又称显示核心、视觉处理器、显示芯片，是一种专门在个人电脑、工作站、游戏机和一些移动设备（如平板电脑、智能手机等）上做图像和图形相关运算工作的微处理器。

BIST: BIST(Built-in Self Test)叫内建自测试技术，是在设计时在电路中植入相关功能电路用于提供自我测试功能的技术，以此降低器件测试对自动测试设备（ATE）的依赖程度。

PPA: PPA (Power、Performance、Area)是衡量芯片设计质量的重要指标。

SoC：System on Chip的缩写，称为系统级芯片，也有称片上系统，意指它是一个产品，是一个有专用目标的集成电路，其中包含完整系统并有嵌入软件的全部内容。同时它又是一种技术，用以实现从确定系统功能开始，到软/硬件划分，并完成设计的整个过程。

SIMD：SIMD全称Single Instruction Multiple Data，单指令多数据流，能够复制多个操作数，并把它们打包在大型寄存器的一组指令集。

TLB：转译后备缓冲器，也被翻译为页表缓存、转址旁路缓存，为CPU的一种缓存，由存储器管理单元用于改进虚拟地址到物理地址的转译速度。当前所有的桌面型及服务器型处理器（如 x86）皆使用TLB。TLB具有固定数目的空间槽，用于存放将虚拟地址映射至物理地址的标签页表条目。

DMA：DMA(Direct Memory Access，直接存储器访问) 是所有现代电脑的重要特色，它允许不同速度的硬件装置来沟通，而不需要依赖于 CPU 的大量中断负载。否则，CPU 需要从来源把每一片段的资料复制到暂存器，然后把它们再次写回到新的地方。在这个时间中，CPU 对于其他的工作来说就无法使用。

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2022届试题

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一、企业知识题：

1、芯原商业模式SiPaaS中第二个S指的是（） A. Solution B. Silicon C. Series D. Service

2、芯原的企业文化是（） A. 公正、友爱、分享、快乐| B. 公正、关爱、分享、快乐 C. 平等、关爱、分享、快乐 D. 诚信、关爱、分享、快乐

二、智力题：

2、判断？填（） $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-TQgJ6M5M-1631759125586)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915102834753.png)]$

A.10 B.14 C.15 D.11

3、下面四个所给出的选项中，每一个选项的盒子不能由左边给定的图形做成：（） $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-1rmojVxs-1631759125587)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915104045147.png)]$

4、如图所示的飞镖盘，如果连投四支飞镖，得到的得分85，请问有多少种投法：（） $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-d4laKN4Y-1631759125588)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915104849279.png)]$

A. 14 B. 12 C. 9 D. 8 E. 6

5、一位酒商有6桶葡萄酒和啤酒，容量分别位30升、32升、36升、38升、40升、62升，其中5桶装着葡萄酒，一桶装着啤酒，第一位顾客买走了两桶葡萄酒，第二位顾客所买葡萄酒则是第一位顾客的两倍，请问哪一桶装着啤酒； A. 40升 B. 36升 C. 38升 D. 32升 E. 30升 F. 62升

三、技术多选题：

1、Which of the following statements are TRUE about "PPA"

A. Power B. Area C. Place&Route D. Performance E. Automatic

2、Which of the following statements are TRUE about Synthesis? A. The tighter the constraints on the synthesis , the better to leave enough margin for the back-end implementation. B. Usually, the target library used in Synthesis is the typical corner library. C. The input of Synthesis include RTL files, library files , SDC file and UPF file... D. The Synthesis steps include translation , mapping and optimization.

3、Which of the following statements are TRUE about power? A. Power reporting should read simulation waveform file if it exists. B. Power reporting should read SDC file if it exists. C. Power types include dynamic power and static power. D. The significance of power consumption is lower than design performance. E. power reporting should read SPEF file if it exists.

4、Why we need post-sim when have finished the STA and formal check? A. It can cover more timing corner. B. It can check asynchronous logic , while STA can't C. It can check timing more accurate D. It can check the design integrity

四、技术单选题：

1、Which method is NOT used to decrease dynamic power? A. Clock gating B. use Low VT cell C. lower frequency D. lower voltage

2、Verilog has four loop descriptions: for, while, repeat, forever, Which one can't be comprehensive? ( ) A、forever B、repeat C、while D、For

3、There is a set-associate Data Cache :total Cache size is 4k Byte ,each cache line size is 32 bytes, Assume read/write address bit width is 32 and each address read/write 1-byte from/to cache . Which cache configuration is right in the following? A. Cache Tag = addr[31:9] ; Index = addr[8:5]; Offset = addr[4:0] B. Cache Tag = addr[31:8] ; Index = addr[7:5]; Offset = addr[4:0] C. Cache Tag = addr[31:8] ; Index = addr[7:5]; Offset = addr[4:0] D. Cache Tag = addr[31:9] ; Index = addr[8:4]; Offset = addr[3:0]

4、To sync pulse signal from high frequency clock domain to low frequency clock domain , which is better? A. Based on the pulse to generate a toggle signal , with two register B. With async fifo C. Extend the pluse to two high freq clock cycles and sync the extended pulse signal D. With handshake mechanism

5、Please choose the high diagram inside ??? block according to the timing waveform Notes: CLK1 network is ideal with 0 delay; the delay CK to QN of DFF is 1/10 T of CLK1; $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-0HRJ7WsJ-1631759125588)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915160231630.png)]$

A. $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-nFCaEf0K-1631759125588)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915160300783.png)]$

B. $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-msaaUsjM-1631759125589)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915160359415.png)]$

C. $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-w11m7sxU-1631759125589)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915160425568.png)]$

D. $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-6cvgJUT0-1631759125590)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915160454721.png)]$

6、In below UVM components , which one is not belonging to agent? A. Monitor B. Driver C. Scoreboard D. Sequencer

7、In system verilog , there are a lot of array types . In below definition ,which is dynamic array A. bit [3:0] x_arr[string c] B. bit [3:0] x_arr[$] C. bit [3:0] x_arr[ ] D. bit[3:0] x_arr[5]

8、In RTL function simulation ,which one is not code coverage A. cress B. Condition C. Fsm D. line

9、Please Select the right throughput and latency value of below pipeline system . Assumption: Pipe_2 can only work when data from Pipe_1A and Pipe_1B both arrive. LT-stands for latency which is in unit of cycles TP-stands for throughput which is in unit of bits/cycle $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-Q1U0qro4-1631759125590)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915162412863.png)]$

A. LT = 12, TP =6; B. LT = 14, TP =6; C. LT = 12, TP =4; D. LT = 5, TP =4;

10、Please select the right display content below Verilog code

integer A,B;
initial begin
    A = 5;  B = 3;
    #1;
    A <= 4; B <= A;
    $display("CP1:A=%1d,B=%1d",A,B);
    #1;
    A <= B; B = A;
    $display("CP2:A=%1d,B=%1d",A,B);
    #1;
    $display("CP3:A=%1d,B=%1d",A,B);

A. CP1:A=5,B=3 CP2:A=4,B=5 CP3:A=5,B=5 B. CP1:A=5,B=4 CP2:A=4,B=4 CP3:A=5,B=5 C. CP1:A=5,B=3 CP2:A=4,B=5 CP3:A=5,B=4 D. CP1:A=5,B=3 CP2:A=4,B=4 CP3:A=5,B=4

11、In below design , the delay assumptions are as: ① Clock period = 20ns ② Clock uncertainty = 0.5ns ③ FF Cell delay = 1.5ns ④ FF Setup = 1.1 ns ⑤ FF hold = 0.4 ns Please select the right setup slack T_setup and hold slack T_hold $[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-L2QCe4tg-1631759125591)(C:\Users\zengxin\AppData\Roaming\Typora\typora-user-images\image-20210915165238149.png)]$