题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    parameter s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
    reg [1:0] sta,nsta;
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            sta <= s0;
        end else begin
            sta <= nsta;
        end
    end
    
    always @(*) begin
        nsta = sta;
        case (sta) 
            s0 : nsta = data ? s1 : s0;
            s1 : nsta = data ? s2 : s1;
            s2 : nsta = data ? s3 : s2;
            s3 : nsta = data ? s0 : s3;
        endcase
    end
    
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            flag <= 1'b0;
        end else if (sta==s3 && data==1'b1) begin
            flag <= 1'b1;
        end else begin
            flag <= 1'b0;
        end
    end
//*************code***********//
endmodule