题解 | #优先编码器电路①#

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

    always @(*) begin
        case(I_n)
            9'b111111111: Y_n = 4'b1111;
            9'b011111111: Y_n = 4'b1110;
            default: begin
                if(I_n[8] == 0)
                    Y_n = 4'b0110;
                else begin
                    if(I_n[7] == 0)
                        Y_n = 4'b0111;
                    else begin
                        if(I_n[6] == 0)
                            Y_n = 4'b1000;
                        else begin
                            if(I_n[5] == 0)
                                Y_n = 4'b1001;
                            else begin
                                if(I_n[4] == 0)
                                    Y_n = 4'b1010;
                                else begin
                                    if(I_n[3] == 0)
                                        Y_n = 4'b1011;
                                    else begin
                                        if(I_n[2] == 0)
                                            Y_n = 4'b1100;
                                        else begin
                                            if(I_n[1] == 0)
                                                Y_n = 4'b1101;
                                            else begin
                                                if(I_n[0] == 0)
                                                    Y_n = 4'b1110;
                                            end
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
        endcase
    end
endmodule