题解 | #输入序列不连续的序列检测#

module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg [3:0]da; always@(posedge clk or negedge rst_n) if(!rst_n) da <= 4'b0; else if(data_valid) da <= {da[2:0], data}; else da <= 4'b0; always@(posedge clk or negedge rst_n)begin if(!rst_n) match <= 0; else if({da[2:0], data} == 4'b0110 && data_valid) match <= 1; else match <= 0; end endmodule