题解 | #序列发生器#
占空比50%的奇数分频
http://www.nowcoder.com/practice/ccfba5e5785f4b3f9d7ac19ab13d6b31
根据题意7分频，实际上是第一次电平变化经历了4个上升沿+3个下降沿，第二次电平变化是4个下降沿+3个上升沿，所以用两个计数器就行了。分别对上升沿和下降沿进行计数，计数总共到7就可以让输出信号取反。 代码如下：
`timescale 1ns/1ns
module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 );
//****code reg[3:0]count_1; reg[3:0]count_2; reg[1:0] data;
always @(posedge clk_in or negedge rst)
if (!rst)begin
count_1 <= 0;
count_2 <= 0;
data <= 0;
end
else
count_1 <= count_1 + 1;
always @(negedge clk_in or negedge rst)
if (!rst)begin
count_1 <= 0;
count_2 <= 0;
data <= 0;
end
else
count_2 <= count_2 + 1;
always @(*)begin
if(count_1+count_2 == 7)begin
count_1 = 0;
count_2 = 0;
data = ~data;
end
else
data = data;
end
assign clk_out7 = data;
//**code// endmodule
