题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    reg[2:0]cnt;
    reg[5:0]data_tmp;
    always @(posedge clk&nbs***bsp;negedge rst_n)
        if(~rst_n)
            ready_a <= 1'b0;
        else
            ready_a <= 1'b1;
    
    always @(posedge clk&nbs***bsp;negedge rst_n)
        if(~rst_n)
            cnt <= 0;
        else if(ready_a && valid_a && cnt==3'd5)
            cnt <= 0;
        else if(ready_a && valid_a)
            cnt <= cnt + 1'b1;
    
    always @(posedge clk&nbs***bsp;negedge rst_n)
        if(~rst_n)
            data_tmp <= 0;
        else if(ready_a && valid_a)
            data_tmp <= {data_a,data_tmp[5:1]};
    
    always @(posedge clk&nbs***bsp;negedge rst_n)
        if(~rst_n)begin
            valid_b <= 0;
            data_b <= 0;
        end else if(ready_a && cnt==3'd5 && valid_a)begin
            data_b <= {data_a,data_tmp[5:1]};//注意此处不是data_tmp,因为data_tmp在下一个valid_a时才有效
            valid_b <= 1;
        end else
            valid_b <= 0;
endmodule