题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    parameter   S0 = 4'b0001,
                S1 = 4'b0010,
                S2 = 4'b0100,
                S3 = 4'b1000;
    
reg    [3:0]    st_cur;
reg    [3:0]    st_next;

always@(posedge clk or negedge rst)begin 
    if(!rst)begin 
       st_cur <= 4'b0; 
    end
    else    begin 
       st_cur <= st_next; 
    end
end

always@(*)begin 
    case(st_cur)
        S0 : st_next = data? S1:S0;
        S1 : st_next = data? S2:S1;
        S2 : st_next = data? S3:S2;
        S3 : st_next = data? S0:S3;
        default : st_next = S0;    
    endcase
end

always@(posedge clk or negedge rst)begin
    if(!rst)begin 
       flag <= 1'b0; 
    end
    else    if((st_cur == S3) && (data))begin 
        flag <= 1'b1;
    end
    else    begin 
       flag <= 1'b0; 
    end
end
//*************code***********//
endmodule