题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

reg    [3:0]    num_reg;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin 
       num_reg <= 4'd0; 
    end
    else    if((mode) && (num_reg == 4'd9))begin 
       num_reg <= 4'd0; 
    end
    else    if((!mode) && (num_reg == 4'd0))begin
       num_reg <= 4'd9; 
    end
    else    if(mode)begin 
       num_reg <= num_reg + 1'b1; 
    end
    else    if(!mode)begin 
       num_reg <= num_reg - 1'b1; 
    end   
end

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
       zero <= 1'b0; 
    end
    else    if(num_reg == 4'd0)begin 
       zero <= 1'b1; 
    end
    else    begin 
        zero <= 1'b0;
    end       
end  

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
       number <= 4'd0; 
    end
    else    begin 
       number <= num_reg; 
    end
end

endmodule