题解 | #边沿检测#

`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a,

output reg rise,
output reg down

);

reg b;
always @ (posedge clk or negedge rst_n) begin
    if (! rst_n) begin
        rise <= 0;
        down <= 0;
        b <= a;
    end
    else 
        if (a - b == 1) begin
            b <= a;
            rise = 1;
            down <= 0;
        end
        else if (b - a == 1) begin
            b <= a;
            down = 1;
            rise <= 0;
        end
        else begin
            rise <= 0;
            down <= 0;
            b <= a;
        end
    end

endmodule