题解 | #数据串转并电路#

声明一个计数器和一个临时变量可以解决
`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    
    reg    [5:0]    data_b_temp;
    
    reg    [2:0]    data_cnt;
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_cnt <= 3'b0;
        else
            begin
                if(valid_a)
                    begin
                        if(data_cnt == 3'd5)
                            data_cnt <= 3'b0;
                        else
                            data_cnt <= data_cnt + 1'b1;
                    end
                else
                    data_cnt <= data_cnt;
            end
    end
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            ready_a <= 1'b0;
        else
            ready_a <= 1'b1;
    end
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_b_temp = 6'b0;
        else
            begin
                if(valid_a)
                    data_b_temp = {data_a , data_b_temp[5:1]};
                else
                    data_b_temp = data_b_temp;
            end
    end
        
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            begin
                data_b <= 6'b0;
                valid_b <= 1'b0;
            end
        else if(data_cnt == 3'd5)
            begin
                data_b <= {data_a , data_b_temp}; //这里主要是上面的temp信号存在一个滞后，所以若在这里的5取一个直接等于temp值，那就是上一个的值，所以需要在这里进行一个拼接作为输出
                valid_b <= 1'b1;
            end
        else
            begin
                data_b <= data_b;
                valid_b <= 1'b0;
            end
    end
    
endmodule