题解 | #数据串转并电路#
数据串转并电路
https://www.nowcoder.com/practice/6134dc3c8d0741d08eb522542913583d
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] data_reg;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_reg <= 'd0;
end
else begin
data_reg <= (valid_a & ready_a)?{data_a,data_reg[5:1]}:data_reg;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 'd0;
end
else begin
cnt <= (valid_a & ready_a)?((cnt=='d5)?'d0:(cnt+'d1)):cnt;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_b <= 1'b0;
ready_a <= 1'b0;
data_b <= 'd0;
end
else begin
valid_b <= (cnt=='d5);
ready_a <= 1'b1;
data_b <= (cnt=='d5)?{data_a,data_reg[5:1]}:data_b;
end
end
endmodule
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