题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
	reg [1:0]cnt;
	reg flag;
	reg clk1;
	reg clk2;


	always@(posedge clk or negedge rst)begin
		if(!rst)
			cnt <= 'b0;
		else if(flag == 0)
			cnt <= 'b0;
		else if(cnt == 2'd1)
			cnt <= 'b0;
		else 
			cnt <= cnt + 1'b1;
	end

	always@(posedge clk or negedge rst)begin
		if(!rst)begin
			clk1 <= 1'b0;
			flag <= 0;
		end
		else if(flag == 0)begin
			clk1<=1;
			flag <= 1;
		end
		else if(cnt == 2'b01)
			clk1 <= ~clk1;
		else 
			clk1 <= clk1;
	end

	always@(posedge clk or negedge rst)begin
		if(!rst)
			clk2 <= 0;
		else if(cnt == 2'd0 && clk1 == 1'b1)
			clk2 <= 0;
		else 
			clk2 <= 1;
	end

	always@(*)begin
		clk_out <= clk1 && clk2;
	end



//*************code***********//
endmodule