题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant ,
output reg [10:0]out
);
//*************code***********//

reg [1:0] cur_st;
reg [1:0] nxt_st;

reg [7:0] d_vld;

parameter 
          ONE_MUL = 3'd0,
          THR_MUL = 3'd1,
          SEV_MUL = 3'd2,
          EGH_MUL = 3'd3;

    always @(posedge clk or negedge rst) begin
        if(rst == 1'b0)
            cur_st <= 3'd0;
        else
            cur_st <= nxt_st;
    end

    always @(*)(1444584) begin
        case(cur_st)
            ONE_MUL: nxt_st <= THR_MUL;
            THR_MUL: nxt_st <= SEV_MUL;
            SEV_MUL: nxt_st <= EGH_MUL;
            EGH_MUL: nxt_st <= ONE_MUL;
            default: nxt_st <= ONE_MUL;
        endcase

    end

    always @(posedge clk or negedge rst) begin 
        if(rst == 1'b0)begin
            out <= 11'd0;
            input_grant <= 1'd0;
        end
        else begin        
            case(cur_st)
                ONE_MUL: begin
                            out <= d;
                            input_grant <= 1'd1;
                end
                THR_MUL: begin
                            out <= (d_vld<<2)-d_vld;
                            input_grant <= 1'd0;
                end
                SEV_MUL: begin
                            out <= (d_vld<<3)-d_vld;
                            input_grant <= 1'd0;
                end
                EGH_MUL: begin
                            out <= (d_vld<<3);
                            input_grant <= 1'd0;
                end
                default: begin 
                            out<= 11'd0;
                            input_grant <= 1'd0;
                end
            endcase
        end
    end
    
    always @(*)(1444584) begin 
        case(cur_st)
                ONE_MUL: d_vld <= d;
                THR_MUL: d_vld <= d_vld;
                SEV_MUL: d_vld <= d_vld;
                EGH_MUL: d_vld <= d_vld;
                default: d_vld <= d;
        endcase
    end

//*************code***********//
endmodule

代码可能写的不太好，但是修改bug的思路重要。最开始给out输出的输入全部是d,后来想 状态机的每个状态d输入不一定都有效，因此需要瞄准one_mul阶段的输入，让其在状态机整个过程保持不变。