题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [4:0] out;
reg validout;
reg [15:0] d_vld;

always @(posedge clk or negedge rst)begin
    if(rst == 1'b0)
        out <= 5'd0;
    else begin
        case(sel)
            2'd0: out <= 5'd0;
            2'd1: out <= d_vld[3:0] + d_vld[7:4];
            2'd2: out <= d_vld[3:0] + d_vld[11:8];
            2'd3: out <= d_vld[3:0] + d_vld[15:12];
        endcase
    end
end

always @(posedge clk or negedge rst)begin
    if(rst == 1'b0)
        validout <= 1'd0;
    else begin
        case(sel)
            2'd0: validout <= 0;
            2'd1: validout <= 1;
            2'd2: validout <= 1;
            2'd3: validout <= 1;
        endcase
    end
end

always @(posedge clk or negedge rst)begin
    if(rst == 1'b0)
        d_vld <= 5'd0;
    else begin
        case(sel)
            2'd0: d_vld <= d;
            2'd1: d_vld <= d_vld;
            2'd2: d_vld <= d_vld;
            2'd3: d_vld <= d_vld;
        endcase
    end
end



//*************code***********//
endmodule


测试文件


`timescale 1ns/1ns



module testbench();
  reg clk       ;
  reg rst       ;
  reg [15:0] d  ;
  reg [1:0] sel ;
  wire [4:0] out;
  wire validout ;

  data_cal data_cal_inst(
    .clk        (clk     ),
    .rst        (rst     ),
    .d          (d       ),
    .sel        (sel     ),
    .out        (out     ),
    .validout   (validout)
  );
    
    initial clk = 1;
    always #5 clk = ~clk;

    initial begin
      rst = 1'b0;
      #11;
      rst = 1'b1;
    end

    initial begin
      sel = 2'd0;
      #30;
      sel = 2'd2;
      #30;
      sel = 2'd1;
      #30;
      sel = 2'd0;
      #10;
      sel = 2'd3;
    end

    initial begin
      d = 16'd0;
      #20;
      d = 16'b1000010000100001;
      #40;
      d = 16'b1000010000100011;
      #50;
      d = 1000010000100111;
    end


    always begin
      #100;
      if($time >= 1000)
        $finish;
    end
 
  initial begin
    $dumpfile("out.vcd");
    // This will dump all signal, which may not be useful
    //$dumpvars;
    // dumping only this module
    //$dumpvars(1, testbench);
    // dumping only these variable
    // the first number (level) is actually useless
    $dumpvars(0, testbench);
end  
    
endmodule