题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	parameter DW = 4'd9,
			  SEQ1 = 3'b011,
			  SEQ2 = 3'b110;

	reg [DW-1:0] data_temp;

	always @(posedge clk or negedge rst_n)begin
		if(rst_n == 1'b0)
			data_temp <= 9'd0;
		else
			data_temp <= {data_temp[DW-1:0],a};
	end
  
	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			match <= 1'b0;
		else if(data_temp[DW-1:DW-3] == SEQ1 && data_temp[DW-7:0] == SEQ2)
			match <= 1'b1;
		else
			match <= 1'b0;
	end
endmodule