题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output  match,
	output  not_match
	);

	parameter DW = 3'd6,
			  SEQ = 6'b011100;

	reg [5:0] data_temp;
	reg [2:0] cnt;
	reg [2:0] cnt_r;
	
	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_temp <= 6'd0;
		else
			data_temp <= {data_temp[DW-2:0],data};
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			cnt <= 3'd0;
		else if(cnt == 3'd5)
			cnt <= 3'd0;
		else
			cnt <= cnt + 1'b1;
	end
	
	always @(posedge clk or negedge rst_n) begin
	   if(rst_n == 1'b0)
	       cnt_r <= 3'd0;
	   else
	       cnt_r <= cnt;
	end
		
	assign match = data_temp == SEQ && cnt_r == 3'd5;
	assign not_match = data_temp != SEQ && cnt_r == 3'd5;
		
endmodule