题解 | #位拆分与运算#

有时序图可知，validout与out为组合逻辑输出。 当sel等于0时，上升沿采样d的值。

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg[15:0]d_reg;
always@(posedge clk or negedge rst)
    if(!rst)
        d_reg <= 16'b0;
    else if(sel == 2'b00)
        d_reg <= d;
    else
        d_reg <= d_reg;

assign validout = (sel == 2'b0) ? 1'b0 : 1'b1;
assign out = (sel == 2'd0)? 5'b0:
             (sel == 2'd1)? d_reg[3:0] + d_reg[7:4]:
             (sel == 2'd2)? d_reg[3:0] + d_reg[11:8]:
             (sel == 2'd3)? d_reg[3:0] + d_reg[15:12]: 5'b0;

//*************code***********//
endmodule