题解 | #串行进位加法器#

`timescale 1ns/1ns


module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire c_1;
wire c_2;
wire sum_1;

add_half add_half_1(
   .A   (A),
   .B   (B),
         
   .S   (sum_1),
   .C   (c_1)  
);
add_half add_half_2(
   .A   (sum_1),
   .B   (Ci),
         
   .S   (S),
   .C   (c_2)  
);

assign Co = c_1 | c_2;
endmodule
/******************************************************************/

module add_4(
   input         [3:0]  A   ,
   input         [3:0]  B   ,
   input                Ci  , 

   output	wire [3:0]  S   ,
   output   wire        Co   
);

    wire [4:1] Co_add4;

    add_full inst0(
        .A          (A[0])  ,
        .B          (B[0])  ,
        .Ci         (Ci)  , 

        .S          (S[0])  ,
        .Co         (Co_add4[1])   
);

    add_full inst1(
        .A          (A[1])  ,
        .B          (B[1])  ,
        .Ci         (Co_add4[1])  , 

        .S          (S[1])  ,
        .Co         (Co_add4[2])   
);

    add_full inst2(
        .A          (A[2])  ,
        .B          (B[2])  ,
        .Ci         (Co_add4[2])  , 

        .S          (S[2])  ,
        .Co         (Co_add4[3])   
);

    add_full inst3(
        .A          (A[3])  ,
        .B          (B[3])  ,
        .Ci         (Co_add4[3])  , 

        .S          (S[3])  ,
        .Co         (Co_add4[4])   
);

assign Co = Co_add4[4];




endmodule