题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
//data_in_old
reg [23:0] data_in_old;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) data_in_old <= 0;
	else if(valid_in) 
		data_in_old <= (data_cnt==4'd5 || data_cnt==4'd10)? data_in : data_in_old;
end
//data_out
reg [127:0] data_out_reg;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		data_out_reg <= 0;
	else if(valid_in)
		data_out_reg <= (data_cnt==4'd5)? {data_out_reg[119:0],data_in[23:16]} 
				 	: ((data_cnt==4'd10)? {data_in_old[15:0],data_out_reg[95:0],data_in[23:8]}
						: ((data_cnt==4'd15)? {data_in_old[7:0],data_out_reg[95:0],data_in}
							: {data_out_reg[103:0],data_in}
							)
						);					
end
// assign data_out = (data_cnt==4'd0 || data_cnt==4'd6 || data_cnt==4'd11)? data_out_reg : data_out;
always@(data_out_reg, rst_n) begin
	if(!rst_n) data_out = 0;
	else if (data_cnt==4'd0 || data_cnt==4'd6 || data_cnt==4'd11)
		data_out = data_out_reg;
	else data_out = data_out;
end
//cnt
reg [3:0] data_cnt;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		data_cnt <= 0;
	else  if(valid_in)
		data_cnt <= data_cnt+1;
end
//valid_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		valid_out <= 0;
	else if ((data_cnt==4'd5 || data_cnt==4'd10 || data_cnt==4'd15) && valid_in)
		valid_out <= 1;
	else valid_out <= 0;
end
endmodule

对比网友们公布的解题思路，减少了data_lock数据暂存的寄存器数量