题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//
localparam s0=0, s1=1, s2=2, s3=3, s4=4, s5=5;

reg [2:0] cur_state;
always@(posedge clk or negedge rst) begin
	if(!rst) begin
		cur_state<=s0;
		// flag <= 0;
	end
	else
		case(cur_state)
		s0 : begin
			cur_state <= (data==1)? s1 : s0;
			// flag <= 0;
		end
		s1 : begin
			cur_state <= (data==0)? s2 : s1;
			// flag <= 0;
		end
		s2 : begin
			cur_state <= (data==1)? s3 : s0;
			// flag <= 0;
		end
		s3 : begin
			cur_state <= (data==1)? s4 : s2;
			// flag <= 0;
		end
		s4 : begin
			if (data==1) begin 
				cur_state <= s5;
				// flag <= 1;
			end
			else begin
				cur_state <= s2;
				// flag <= 0;
			end
		end
		s5 : begin
			cur_state <= (data==0)? s0 : s1;
			// flag <= 0;
		end
		endcase
end
always@(*) begin
	if(!rst)
		flag <= 0;
	else
		flag <= (cur_state==s5);
end
//*************code***********//
endmodule