verilog题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
reg[1:0]mux_out_reg;

always@(*)(1444584) begin
    case(sel) 
        2'b00:begin
            mux_out_reg = d3;
        end
        2'b01:begin
            mux_out_reg = d2;
        end
        2'b10:begin
            mux_out_reg = d1;
        end
        2'b11:begin
            mux_out_reg = d0;
        end
    endcase
end

assign mux_out=mux_out_reg;



//*************code***********//
endmodule

`timescale 1ns/1ns
module testbench();
  initial begin
    $dumpfile("out.vcd");
    $dumpvars(0, testbench);
  end 
    reg [1:0]d1,d2,d3,d0,sel;
    initial begin
        d1=0;
        d2=1;
        d3=2;
        d0=3;
        sel=0;
        #5 sel=1;
        #5 sel=2;
		$finish(0);
    end
    mux4_1 t(.d1(d1),
             .d2(d2),
             .d3(d3),
             .d0(d0),
             .sel(sel),
             .mux_out(mux_out));
endmodule

case语句要加endcase

always语句中的reg类型才能赋值

testbench要加$finish(0)