题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

reg [1:0] cstate,nstate;

always @ (posedge clk,negedge rst_n) begin
    if(rst_n  == 1'b0) cstate <= 2'b00;
    else  cstate <= nstate;
end

always @ (*) begin
    case(cstate)
        2'b00: 
            begin
                    if(A==1'b0) nstate <= 2'b01;
                    else nstate <= 2'b11;
            end
        2'b01: 
            begin
                    if(A==1'b0) nstate <= 2'b10;
                    else nstate <= 2'b00;
            end
        2'b10: 
            begin
                    if(A==1'b0) nstate <= 2'b11;
                    else nstate <= 2'b01;
            end
        2'b11: 
            begin
                    if(A==1'b0) nstate <= 2'b00;
                    else nstate <= 2'b10;
            end
    endcase
end


assign Y = (cstate == 2'b11) ? 1 :0;
endmodule