题解 | #奇偶校验#

`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//
reg odd;//或者用wire类型 assign语句
always@(*)begin
    odd = ^bus;
end

assign check = sel?odd:!odd;
//*************code***********//
endmodule

testbench如下：

`timescale 1ns/1ns



module testbench();
	reg clk=0;
	always #5 clk = ~clk;  // Create clock with period=10
// A testbench
    
    reg [31:0]bus;
    reg sel;
    initial begin
      sel = 1;
      bus = {$random}%10;
      #10 bus = {$random}%10;
      #10 bus = {$random}%10;
      #10 bus = {$random}%10;

      $finish(0);
    end
    
    odd_sel u1(
      .bus(bus),
      .sel(sel),
      .check(check)
    );
    
//end    
  initial begin
    $dumpfile("out.vcd");
    $dumpvars(0, testbench);
end  
    
endmodule

testbench使用随机数测试

{$random}%10 表示10以内正整数

$random%10 表示-10到10的整数