题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input data,
    output  reg match,
    output reg not_match
    );

	reg [3:0] state_cur,state_next;
    parameter S1 = 4'd1, S2 = 4'd2,S3 = 4'd3,S4 = 4'd4,S5 = 4'd5,S6 = 4'd6,S0 = 4'd0;
	parameter C1 = 4'd7, C2 = 4'd8,C3 = 4'd9,C4 = 4'd10,C5 = 4'd11,C6 = 4'd12;//错误状态
	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
		state_cur <= 1'b0;
		else 
		state_cur <= state_next; 
	end


    always @(*) begin
        case(state_cur)
            S1:state_next = data?S2:C2;
            S2:state_next = data?S3:C3;
            S3:state_next = data?S4:C4;
            S4:state_next = data?C5:S5;
            S5:state_next = data?C6:S6;
            S6:state_next = data?C1:S1;
            S0:state_next = data?C1:S1;
			C1:state_next = C2;
			C2:state_next = C3; 
			C3:state_next = C4; 
			C4:state_next = C5; 
			C5:state_next = C6; 
			C6:state_next = data?C1:S1;  
		endcase
	end

        always @(*) begin
            if((state_cur == S6))
			begin
                match <= 1'b1;
			
			end
            else
			begin
                match <= 1'b0;
			
			end
			end

		always @(*) begin
            if(state_cur == C6)   //注意这里是C5，
			begin
                not_match <= 1'b1;
			end
            else
			begin
                not_match <= 1'b0;
			
			end
			end

endmodule