题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
reg [2:0]sum;
always@( clk or negedge rst)begin
	if(!rst)
		sum <= 3'd0;
	else
		sum <= (out1)?3'd0:sum+{{2'b00,d1}+{1'b0,d2,1'b0}+{d3,2'b00}};
end

always@(posedge clk or negedge rst)begin
	if(!rst)begin
		out1 <= 'd0;
		out2 <= 'd0;
	end
	else begin
		out1 <= (sum  >= 3'd3);
		out2 <= (sum  >= 3'd3)?sum-3'd3:0;
	end

end
//*************code***********//
endmodule