题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);

parameter ram_num = $pow(2,7);
reg [3:0] buff[0 : ram_num-1];
always@(posedge clk or negedge rst_n)  begin
	if(write_en)
		buff[write_addr] <= write_data;
	else
		buff[write_addr] <= 'd0;
end

always @(posedge clk or negedge rst_n)  begin
	if(!rst_n)
		read_data <= 'd0;
	else if(read_en)
		read_data <= buff[read_addr];
end	
endmodule