题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [2:0] curr_st;
reg [2:0] next_st;
parameter S0=3'd0;
parameter S1=3'd1;
parameter S2=3'd2;
parameter S3=3'd3;
parameter S4=3'd4;
parameter S5=3'd5;

always @(posedge clk or negedge rst)begin
	if(~rst)begin
		curr_st<=S0;
	end else begin
		curr_st<=next_st;
	end
end

always @(*)begin
	case(curr_st)
	S0:begin
		next_st=(data==1)?S1:S0;
	end
	S1:begin
		next_st=(data==0)?S2:S1;
	end
	S2:begin
		next_st=(data==1)?S3:S0;
	end
	S3:begin
		next_st=(data==1)?S4:S2;
	end
	S4:begin
		next_st=(data==0)?S2:S1;
	end
	endcase
end

always @(posedge clk or negedge rst)begin
	if(~rst)begin
		flag<=0;
	end else if(curr_st==S4)begin
		flag<=1;
	end else begin
		flag<=0;
	end
end


//*************code***********//
endmodule