题解 | #边沿检测#

//打一拍即可
`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg a_temp0;

    always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
	a_temp0<=0;
	
	end
	else begin
	a_temp0<=a;

	end

	always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
	rise<=0;
	down<=0;
	end
	else if(a&!(a_temp0))begin
	rise<=1;
	down<=0;end
	else if(a_temp0&!a)begin
	down<=1;
	rise<=0;
	end
	else begin
		rise<=0;
		down<=0;
	end
	end
	


endmodule