题解 | #输入序列连续的序列检测#

/*
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [7:0] sq;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	sq <= 'd1;
	else
	sq <= {sq[6:0],a};
end

always@(posedge clk or negedge rst_n)
	if(!rst_n)
	match <= 'd0;
	else
 	match <= (sq == 8'b01110001) ? 1: 0;
  
endmodule
*/
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [4:0] cs;
reg [4:0] ns;
parameter IDLE = 'd0,
S1 = 'd1,
S2 = 'd2,
S3 = 'd3,
S4 = 'd4,
S5 = 'd5,
S6 = 'd6,
S7 = 'd7,
S8 = 'd8;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	cs<= 'd0;
	else
	cs <= ns;
end

always@(*)begin
	ns = IDLE;
	case(cs)
		IDLE:ns = a ? IDLE:S1;
		S1:  ns = a ? S2:S1;
		S2:  ns = a ? S3:S1;
		S3:  ns = a ? S4:S1;
		S4:  ns = a ? IDLE:S5;
		S5:  ns = a ? S2:S6;
		S6:  ns = a ? S2:S7;
		S7:  ns = a ? S8:S1;
		S8:  ns = a ? IDLE:S1;
	endcase
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		match <= 'd0;
	// else if(ns == S8)
	else if(cs == S8)
		match <= 'd1;
	else
		match <= 'd0;
end


  
endmodule

用ns判断寄存输出怎么能算错呢？？？