题解 | #无占空比要去的奇数分频#

//奇数分频3/5 占空比
`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    reg [3:0]cnt;
    reg clk_out;

    always@(posedge clk_in  or negedge rst)
    begin
    if(!rst)begin
    cnt<=0;
    end
    else if(cnt==4)
    begin
    cnt<=0;
    end
    else begin
    cnt<=cnt+1;
    end
    end

    always@(posedge clk_in  or negedge rst)
    begin
    if(!rst)begin
    clk_out<=0;
    end
    else if(cnt==0|cnt==2)
    begin
    clk_out<=~clk_out;
    end
    else begin
    clk_out<=clk_out;
    end
    end

    assign clk_out5=clk_out;


//*************code***********//
endmodule