题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [5:0] data;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data <= 6'b100000;
		valid_b <= 'd0;
		ready_a <= 0;
	end
	else begin
		ready_a <= 1;
		if(valid_a)begin
			data <= (valid_b)?{data_a,5'b10000} : {data_a,data[5:1]};
			valid_b<=(valid_b)? 0: data[0];
		end
		else
		valid_b <= 0;
	end
end

always@(*)begin
	if(!rst_n)
	data_b = 'd0;
	else
	data_b = (valid_b) ? data:data_b;
end

endmodule