题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);

reg [3:0] data_out;
always @(clk or negedge rst_n)
begin
	if(!rst_n)
		data_out <= 4'b0000;
	else 
		case (addr)
			8'b0000_0000:
				data_out <= 4'b0000;
			8'b0000_0001:
				data_out <= 4'b0010;
			8'b0000_0010:
				data_out <= 4'b0100;
			8'b0000_0011:
				data_out <= 4'b0110;
			8'b0000_0100:
				data_out <= 4'b1000;
			8'b0000_0101:
				data_out <= 4'b1010;
			8'b0000_0110:
				data_out <= 4'b1100;
			8'b0000_0111:
				data_out <= 4'b1110;
		endcase 		
end

assign data = data_out;
endmodule