题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a_un;

always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		a_un <= 1'b0;  
	else 
		a_un <= a;

always @(posedge clk or negedge rst_n)
	if(!rst_n) begin
		rise <= 1'b0;
		down <= 1'b0;
	end 
	else if(a&&~a_un)
		rise <= 1'b1;
	else if(~a&&a_un)
		down <= 1'b1;
	else begin
		rise <= 1'b0;
		down <= 1'b0;
	end
endmodule