题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
reg q,q1,q2,q3;

always@(posedge clk_fast or negedge rst_n)begin
	if(!rst_n)
	q<= 'd0;
	else
	q<= data_in? ~q:q;
end

always@(posedge clk_slow or negedge rst_n)begin
	if(!rst_n)begin
	q1<= 'd0;
	q2<= 'd0;
	q3<= 'd0;
	end
	else begin
	q1<= q;
	q2<= q1;
	q3<= q2;
	end
end

assign dataout = q2 ^ q3;

endmodule