题解 | #不重叠序列检测#该代码与题目要求不符合

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

// 011100
//
reg [5:0] a_ray;
reg [2:0] a_num;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        a_ray <= 0;
        match <= 0;
        not_match <= 0;
        a_num <= 0;
    end
    else begin
        if (a_num==6) begin
            a_ray <= {5'b00000,data};
            a_num <= 1;
			match <= 0;
            not_match <= 0;
        end
        else begin
            a_ray <= {a_ray[4:0],data};
            a_num <= a_num + 1;
            match <= 0;
            not_match <= 0;
        end
    end
end
always @(a_num) begin
    if (a_num==6) begin
        if (a_ray==6'b011100)
            match <= 1;
        else
            not_match <= 1;
    end
end
endmodule

题目时序图出现错误。match需提前一个时钟周期指示，即指示信号与第6信号同时显示。

题目要求用状态机实现，该代码未使用状态机。