题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
reg [3:0] cnt;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	cnt <= 'd0;
	else 
	cnt <= set?set_num : cnt + 1;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	number <= 'd0;
	else 
	number <= cnt;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	zero <= 'd0;
	else
	zero <= (cnt == 'd0) ? 1: 0;
end

endmodule

m一下，解析挺简单的，但是想起来竟然有点绕。。。