题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
reg [5:0] wave_num;
reg [1:0] wave_choise_ray;
reg wave_down;
// 20,21,40
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        wave <= 5'b0;
        wave_num <= 6'b0;
        wave_down <= 1;
		end
    else begin
        wave_choise_ray <= wave_choise;
        case(wave_choise)
            2'b0: if (wave_choise_ray==wave_choise) begin
                        wave_num <= (wave_num<9)?(wave_num+1):0;
                        wave <= (wave_num<9)?wave:
                                ((|wave)?5'b0:5'b10100);
                    end
                    else begin
                        wave_num <= 1;
                        wave <= 5'b00000;
                    end 
            2'b1: if (wave_choise_ray==wave_choise) begin
                        wave_num <= (wave_num<20)?(wave_num+1):0;
                        wave <= (wave_num<20)?(wave+1):5'b0;
                    end
                    else begin
                        wave_num <= 0;
                        wave <= 5'b0;
                    end
			2'b10:  if (wave==5'b10100) begin
						wave <= 5'b10011;
						wave_down <= 1;
					end
					else if (wave==5'b0) begin
						wave <= 5'b00001;
						wave_down <= 0;
					end
					else if (wave_down) 
						wave <= wave-1;
					else
						wave <= wave+1;
                
        endcase          
    end
end
  
endmodule