题解 | #自动贩售机2#

`timescale 1ns/1ns
module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
    
    
parameter   idle     =   7'b000_0001,
   			half     =   7'b000_0010,
  	 		one      =   7'b000_0101,
   			one_half =   7'b000_1000,
   			two      =   7'b001_0000,
  			two_half =   7'b010_0000,
   			three    =   7'b100_0000;

wire [1:0]	 pi_money={d2,d1};
reg  [6:0]   state, next_state;

always@(posedge clk or negedge rst) begin
    if(!rst)
         state <= idle;
    else
         state <= next_state;
    end

always@(*) begin
    if(sel) begin   //饮料2，2.5元的
        case(state) //d1表示投入0.5元，d2表示投入1元

            idle: case(pi_money)
						
						2'b01: next_state = half;
						2'b10: next_state = one;
						default: next_state = next_state;
				endcase
				
            half: case(pi_money)
						
						2'b01: next_state = one;
						2'b10: next_state = one_half;
						default: next_state = next_state;
				endcase

            one: case(pi_money)
						
						2'b01: next_state = one_half;
						2'b10: next_state = two;
						default: next_state = next_state;
				endcase

            one_half: case(pi_money)
						
						2'b01: next_state = two;
						2'b10: next_state = two_half;
						default: next_state = next_state;
				endcase

            two : case(pi_money)
						
						2'b01: next_state = two_half;
						2'b10: next_state = three;
						default: next_state = next_state;
				endcase

            two_half: next_state = idle;
            three   : next_state = idle;
            default : next_state = idle;
        endcase
    end
    else begin
        case(state)

            idle    : case(pi_money)
						
						2'b01: next_state = half;
						2'b10: next_state = one;
						default: next_state = next_state;
			endcase

            half    : case(pi_money)
						
						2'b01: next_state = one;
						2'b10: next_state = one_half;
						default: next_state = next_state;
			endcase

            one     : case(pi_money)
						
						2'b01: next_state = one_half;
						2'b10: next_state = two;
						default: next_state = next_state;
			endcase

            two     : next_state = idle;
            two_half: next_state = idle;
            three   : next_state = idle;
            default : next_state = idle;
        endcase
    end
    end

    //注意：这种三段式输出要看next_state而不是state！
always@(posedge clk or negedge rst) begin
    if(!rst) begin
        out1  <= 1'b0;
        out2  <= 1'b0;
        out3  <= 1'b0;
    end
    else if(sel) begin  //饮料2, 2.5元的
        out1  <= 1'b0;
        if(next_state == two_half) begin
            out2  <= 1'b1;
            out3 <= 1'b0;
        end
        else if(next_state == three) begin
            out2  <= 1'b1;
            out3 <= 1'b1;
        end
        else  begin
            out2  <= 1'b0;
            out3 <= 1'b0;
        end
    end
    else begin  //饮料1, 1.5元的
        out2  <= 1'b0;
        if(next_state == one_half) begin
            out1  <= 1'b1;
            out3 <= 1'b0;
        end
        else if(next_state == two) begin
            out1  <= 1'b1;
            out3 <= 1'b1;
        end
        else  begin
            out1  <= 1'b0;
            out3 <= 1'b0;
        end
    end
end
    
endmodule