题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
reg     [1:0]   mux_out_reg ;
assign  mux_out = mux_out_reg ;
always @(*) begin
    case(sel) 
        2'd0: begin
            mux_out_reg = d3;
        end
        2'd1: begin
            mux_out_reg = d2 ;
        end
        2'd2: begin
            mux_out_reg = d1 ;
        end
        2'd3: begin
            mux_out_reg = d0 ;
        end
        default :begin
            mux_out_reg = d0 ;
        end
    endcase
end

//*************code***********//
endmodule