题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input 				clk,
	input 				rst_n,
	input 				set,
	input [3:0] 		set_num,
	output reg [3:0]	number,
	output reg 			zero
	);

// 注意：从波形图可以看到，计数器输出number延迟一个时钟周期才输出，因此需要加一个中间计数器num
reg [3:0] num;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		num<=4'd0;
	else if(set==1'b0)
		if(num==4'd15)
			num<=4'd0;
		else
			num<=num+1'b1;
	else 
		num<=set_num;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		zero <=1'b0;
	else if(num==4'd0)
		zero <=1'b1;
	else
		zero <=1'b0;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		number <=4'd0;
	else 
		number<= num ;
end
endmodule