题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
	reg [7:0] data_lock;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_lock <= 0;
		end
		else if(valid_in) begin
			data_lock <= data_in;
		end
		else begin 
			data_lock <= data_lock;
		end
	end

	reg [1:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			cnt <= 0;
		end
		else if(valid_in) begin
			if (cnt == 2) begin
				cnt <= 0;
			end
			else begin
				cnt <= cnt + 1'b1;
			end
		end
		else begin
			cnt <= cnt;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			valid_out <= 0;
		end
		else if(valid_in && (cnt == 2'd1)) begin//在上升沿那一时刻，valid_in为1，cnt为1，持续一个周期后，valid_in变为0，就不满足了
			valid_out <= 1'b1;
		end
		else if(valid_in && (cnt == 2'd2)) begin//在上升沿那一时刻，valid_in为1，cnt为1，持续一个周期后，valid_in变为0，就不满足了
			valid_out <= 1'b1;
		end
		else begin
			valid_out <= 0;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <= 0;
		end
		else if(valid_in) begin
			if(cnt == 2'd1)begin
				data_out = {data_lock,data_in[7:4]};
			end
			else if(cnt == 2'd2) begin
				data_out = {data_lock[3:0],data_in};
			end
			else begin
				data_out <= data_out;
			end
		end
		else begin
			data_out <= data_out;
		end
	end



endmodule