题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [3:0] nstate ,cstate;
always@(posedge clk , negedge rst_n) begin
	if(rst_n == 0)
		cstate <= 'b0;
	else
		cstate <= nstate;
end

always@(*) begin
	case(cstate)
	'd0: 
		if(a == 1'b0)
			nstate = 'd1;
		else
			nstate = 'd0;	
	'd1: 
		if(a == 1'b0)
			nstate = 'd0;
		else
			nstate = 3'd2;	
	'd2: 
		if(a == 1'b0)
			nstate = 'd0;
		else
			nstate = 'd3;	
	'd3: 
		if(a == 1'b0)
			nstate = 'd0;
		else
			nstate = 'd4;
	'd4: 
		if(a == 1'b0)
			nstate = 'd5;
		else
			nstate = 'd0;	
	'd5: 
		if(a == 1'b0)
			nstate = 'd6;
		else
			nstate = 'd2;
	'd6: 
		if(a == 1'b0)
			nstate = 'd7;
		else
			nstate = 'd2;
	'd7: 
		if(a == 1'b0)
			nstate = 'd1;
		else
			nstate = 'd8;
	'd8:
		if(a == 1'b0)
			nstate = 'd1;
		else
			nstate = 'd0;
	default:
			nstate = 'd0;		
	endcase
end

always@(posedge clk , negedge rst_n) begin
	if(rst_n == 0)
		match <= 'b0;
	else if(cstate=='d8)
		match <= 1'b1;
	else 
		match <= 'b0;
end

//assign match = cstate==3'd7 && a == 1'b1;
endmodule