题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

	/*reg [2:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 0;
		end
		else begin
			cnt <= (cnt == 3'd5)? 0: cnt + 1'b1;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data <= 0;
		end
		else begin
			case(cnt) 
				0: data <= 0;
				1: data <= 0;
				2: data <= 1;
				3: data <= 0;
				4: data <= 1;
				5: data <= 1;
				default: data <= 0;
			endcase
		end
	end*/
	


	reg [5:0] data_in_reg;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_in_reg <= 6'b001011;
		end
		else begin
			data_in_reg <= {data_in_reg[4:0],data_in_reg[5]};
		end
	end
	
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data <= 0;
		end
		else begin
			data <= data_in_reg[5];
		end
	end

endmodule