题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
always@(posedge clk or negedge rst_n)
if(!rst_n)
	c<=9'd0;
else case(select)
0: c<=a;
1: c<=b;
2: c<=a+b;
3: c<=a-b;
default:c<=9'd0;
endcase
endmodule

假如都定义成了有符号数类型 signed，直接加减就可以

如果没定义成signed，就要给符号位扩展，就是把符号位再复制一个放到最高位。