题解 | #输入序列连续的序列检测#

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
  
reg  [7:0] seg;

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		seg <= 8'b0;
	else 
		seg <= {seg[6:0],a};
end

  
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		match <= 1'b0;
	else if(seg == 8'b01110001)
		match <= 1'b1;
	else
		match <= 1'b0;
end
endmodule