题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg  [3:0]memory [7:0];
always@(posedge clk)
begin
memory[0]<=4'd0;
memory[1]<=4'd2;
memory[2]<=4'd4;
memory[3]<=4'd6;
memory[4]<=4'd8;
memory[5]<=4'd10;
memory[6]<=4'd12;
memory[7]<=4'd14;
end
reg [3:0]data;
always@(*)
begin
if(rst_n==1'b0) data<=0;
else data<=memory[addr];
end 
endmodule