题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
reg Y0=0;
reg [1:0]Q=0;
reg [1:0] state, next_state;
 parameter S0=2'b00;
 parameter S1=2'b01;
 parameter S2=2'b10;
parameter S3=2'b11;
always@(posedge clk or negedge rst_n)
begin
  if(!rst_n) state<=S0;
  else  state <= next_state;
end
always@(*)
begin
  case(state) 
    S0:next_state=C?S1:S0;
    S1:next_state=C?S1:S3;
    S2:next_state=C?S2:S0;
    S3:next_state=C?S2:S3;
    default : next_state=S0;
  endcase
end
always@(*)
begin
   if((state==S2&&C==1)|(state==S3&&C==1)|(state==S3&&C==0)) Y0<=1;
   else Y0<=0;
end
assign Y=Y0;
endmodule

状态机的三段式，比较经典，下周需要重复做这题加强记忆。