题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg data_temp;

always@(posedge clk or negedge rst)begin
    if(!rst)begin
        data_temp<=0;
    end else begin
        data_temp<=data^data_temp;
    end
end
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        q<=0;
    end else begin
        q<=data_temp^q;
    end
end

//*************code***********//
endmodule