题解 | #奇偶校验#

`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
reg check_r;
//*************code***********//
always@(*)begin
    case(sel)
        1'b1:check_r=^bus;
        1'b0:check_r=~^bus;
        default:check_r=0;
    endcase
end
assign check=check_r;

//*************code***********//
endmodule