题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
wire S_r,Co_r,Co_r2;
add_half A1(.A(A),.B(B),.S(S_r),.C(Co_r));
add_half A2(.A(S_r),.B(Ci),.S(S),.C(Co_r2));
assign Co=Co_r|Co_r2;
endmodule